Woolcano: An Architecture And Tool Flow For Dynamic Instruction Set Extension On Xilinx Virtex-4 FX

نویسندگان

  • Mariusz Grad
  • Christian Plessl
چکیده

.text .global scalar_prod .type scalar_prod, @function .align 2 scalar_prod: stfs 2, -8(1) ; spill floating-point regs to stack memory stfs 1, -4(1) ; spill FPR1 stfs 4, -16(1) ; spill FPR4 stfs 3, -12(1) ; .... stfs 6, -24(1) stfs 5, -20(1) lwz 3, -8(1) ; load spilled FPR2 from stack to GPR3 lwz 4, -4(1) ; load spilled FPR1 from stack to GPR4 lwz 5, -16(1) ; .... lwz 6, -12(1) udi0fcm 3, 4, 3 ; send operands to operand register lwz 3, -24(1) lwz 4, -20(1) udi0fcm 5, 6, 5 ; send more operands to op register udi2fcm 3, 4, 3 ; send last op & trigger custom inst stw 3, -28(1) ; store results (GPR3) to stack lfs 1, -28(1) ; copying results from stack to FPR1 blr .size scalar_prod,.-scalar_prod source code (ANSI C)

برای دانلود متن کامل این مقاله و بیش از 32 میلیون مقاله دیگر ابتدا ثبت نام کنید

ثبت نام

اگر عضو سایت هستید لطفا وارد حساب کاربری خود شوید

منابع مشابه

An End-to-End Design Flow for Automated Instruction Set Extension and Complex Instruction Selection based on GCC

Extensible processors are application-specific instruction set processors (ASIPs) that allow for customisation through user-defined instruction set extensions (ISE) implemented in an extended micro architecture. Traditional design flows for ISE typically involve a large number of different tools for processing of the target application written in C, ISE identification, generation, optimisation ...

متن کامل

On the Feasibility and Limitations of Just-in-Time Instruction Set Extension for FPGA-Based Reconfigurable Processors

Reconfigurable instruction set processors provide the possibility of tailor the instruction set of a CPU to a particular application. While this customization process could be performed during runtime in order to adapt the CPU to the currently executed workload, this use case has been hardly investigated. In this paper, we study the feasibility of moving the customization process to runtime and...

متن کامل

Self-Reconfiguration of Embedded Systems Mapped on Spartan-3

This paper describes the architecture and design flow of a self-reconfigurable embedded system, mapped on Spartan-3 low-cost FPGA. The proposed design flow combines EDK and ISE software along with an ownmade tool, in order to create a self-reconfigurable system able to map a reconfigurable OPB coprocessor. A fixed area of the FPGA is reserved to accommodate a set of coprocessors whose execution...

متن کامل

Packet Filtering in Gigabit Networks Using FPGAs

Network security is an important aspect for a networked information society. The ever growing datarates of Internet traffic call for dedicated hardware solutions to prevent networks from malicious attacks. Packet filtering belongs to a number of measures to ensure the availability and reliability of networks. Packet filters classify the network traffic by rules and omit those packets that might...

متن کامل

An ASIP architecture framework to facilitate automated design space exploration and synthesis for Iterative Repair solvers

Autonomous dynamic event scheduling, using Iterative Repair techniques such as those employed by CASPER and ASPEN, is an essential component of successful space missions, as it enables spacecraft to adaptively schedule tasks in a dynamic, real-time environment. Event rescheduling is a compute-intensive process. Typical applications involve scheduling hundreds of events that share tens or hundre...

متن کامل

ذخیره در منابع من


  با ذخیره ی این منبع در منابع من، دسترسی به آن را برای استفاده های بعدی آسان تر کنید

برای دانلود متن کامل این مقاله و بیش از 32 میلیون مقاله دیگر ابتدا ثبت نام کنید

ثبت نام

اگر عضو سایت هستید لطفا وارد حساب کاربری خود شوید

عنوان ژورنال:

دوره   شماره 

صفحات  -

تاریخ انتشار 2009